1. Field of the Invention
The present invention generally relates to integrated storage devices and more particularly to an improved dynamic random access memory dielectric structure, and the method for producing the same.
2. Description of the Related Art
DRAM, the dynamic random access memory, is known to have a much higher memory density than the SRAM, or the static random access memory. Usually, in order to achieve a high integration density, either a deep trench-capacitor or a high-k dielectric stack-capacitor cell is employed. Although the deep trench capacitor has a planar surface topography, the depth of the trench has become the limiting factor in preventing the scaling of DRAM exceeding 4 gigabytes. However, the high-k dielectric stack-capacitor cell is limited by the material stability as well as the topography. Here, the stack-capacitor is built on top of the silicon surface. Thus, the resulting non-planar surface has created problems for metallization as well as lithographic patterning. Conversely, the performance of the DRAM that is determined by the MOS device parameters, such as the gate dielectric thickness, channel length and width are now facing physical limitations. For example, MOS devices using conventional thermal oxide as the gate dielectric cannot be thinner than 3 nanometers in order to avoid a reliability concern. Moreover, if the device channel length is shorter than 0.1 micrometers, the result will be suffering from the short channel effect as well as the occurrence of a high-level leakage current.
As the channel width is limited by the chip area, the device performance degrades when the Vdd, the power supply, is reduced below 1 volt. Therefore, in order to replace DRAM with SRAM for cache applications, it is important that the device performance be maintained at its initial level, while the chip size is continuously reduced. In other words, DRAM access time, or cycle time must be in the range of 3 to 5 nanoseconds at low-power conditions. Thus, there is a need to reduce the cost and improve performance of DRAM.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional DRAM structures, the present invention has been devised, and it is an object of the present invention to provide a structure and method for an improved DRAM structure.
The goal of this invention is to (1) improve the performance of DRAM, and (2) reduce the process cost. A new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. It is the first time that a high-k dielectric is used for a deep trench capacitor as well as the support devices. This will not only reduce the trench depth, but also improve the performance of the support devices because the high-k dielectric gate support device will enable a reduction in the equivalent gate oxide thickness, and hence an increase in the gage electrode control of the MOSFET channel, without degrading the reliability and gate leakage current of the thin dielectric device.
Since the high-k dielectric is applied at once, process steps are greatly reduced compared to the case when they are separately applied. The thermal budget is also reduced accordingly, since only one dielectric anneal is needed. The transfer gate of the array devices intentionally use the conventional dielectric to avoid any possibility of charge leakage that is commonly associated with high-k materials. The support devices, which require having a large drivability such as the wordline drivers, the OCDs (off-chip-driver), and the clock drivers, can improve their drivability without using a large device size due to the improved transistor performance of the high-k devices. This gives more room for higher-level and density of integration.
In order to attain the objects suggested above, there is provided, according to one aspect of the invention a method for producing a dynamic random access memory device with a high-k dielectric constant. More specifically, the method deposits a first insulator oxide layer and a passive insulator nitride layer on a substrate. Then, the invention forms multiple deep trench regions on the substrate. The deep trench regions each have exposed surfaces to allow for coating of conductive material. Furthermore, a pair of collars extend from the upper portions of the deep trench regions, and are diametrically opposed to each other. An n+ diffusion region extends on the lower portion of the deep trench region. The n+ diffusion layer for each trench is linked together by an n+ buried layer and is used as the plate node of the capacitor array.
Then, the nitride layer and the oxide layer from the support area of the substrate are removed by dry or wet etchings. Next, a second insulator layer in the form of a high-k dielectric is deposited on the composite, including in the deep trench channel, where the dielectric is used as the trench dielectric as well as the gate dielectric for the support devices. After that, a first conductive layer is deposited above the second insulator layer. Then, a planarization process occurs where the composite is recessed in order to form a planar surface followed by a second recess which lowers the level of the first conductive layer located in the deep trench region.
Next, a second conductive layer in the form of n+ doped polysilicon is deposited above the first conductive layer in the deep trench region to a level flush with an uppermost portion of the composite. Another insulator layer such as nitride is then deposited on top of the composite. Then, several shallow channel isolation regions are formed in the composite such that an upper portion of the shallow trench is above the second conductive layer.
Following that, the exposed first and second insulator layers in the form of nitride layers are removed using a dry or wet etching process. Next, a third conductive layer in the form of doped polysilicon is deposited on top of the composite. Then, a fourth conductive layer in the form of tungsten, or any proper refractory metal is deposited on top of the third conductive layer. The composite gates are then formed to create transfer devices and support devices. This is done by removing any exposed first and third conductive layers from the composite. Next, portions of the substrate are doped to form source and drain regions. Then, contacts are formed on top of the second insulator layer. Finally, a third insulator layer is deposited on top of the composite.